1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. In particular, the present invention relates to an ESD protection circuit suitable for applying in an integrated circuit (IC).
2. Description of the Prior Art
As the scale of devices in ICs has become smaller, the devices have become more vulnerable to Electrostatic discharge (ESD). Hence, ESD has been one of the most important reliability issues for IC products and must be taken into consideration in the design phase of all ICs.
Besides an ESD clamp device, an ESD detection circuit is another critical component in on-chip ESD protection circuits because it highly relates to the ESD protection capability of an on-chip ESD protection circuit. The ESD detection circuit is designed to provide trigger currents to turn on the ESD clamp device when the IC product is under ESD stresses.
A variety of ESD detection circuits were proposed. FIG. 1 illustrates an ESD protection circuit for input pads proposed in the U.S. Pat. No. 6,465,768. Generally, ESD occurs when one pin of an IC is grounded and another pin of the IC contacts an electrostatically pre-charged object. For instance, under positive-to-VSS (PS-mode) ESD stresses, a positive ESD zapping is applied to the input pad in FIG. 1 while the VSS power rail is grounded and the VDD power rail is floating.
Under PS-mode ESD stresses, the positive ESD voltage pulse at the input pad is coupled through the capacitor 102 to the gate terminal 106 of the NMOS 104. When the coupled voltage at the gate terminal 106 of NMOS 104 is greater than the threshold voltage of NMOS 104, NMOS 104 is turned on to conduct some ESD currents from the stressed input pad to the base terminal of the parasitic NPN BJT 114 in NMOS 112, which is formed by the N+ diffusion, P-well region, and N+ diffusion.
With the trigger current injected to the base terminal of the parasitic NPN BJT 114 in NMOS 212, NMOS 212 is turned on to discharge ESD current from the input pad to VSS power rail, and the internal circuit 100 can be protected from being damaged by ESD currents.
Under negative-to-VDD (ND-mode) ESD stresses, the negative ESD zapping is applied to the input pad while the VDD power rail is grounded and the VSS power rail is floating. Under ND-mode ESD stresses, the negative ESD voltage pulse at the input pad is coupled through the capacitor 122 to the gate terminal 126 of the PMOS 124. With the coupled voltage at the gate terminal 126 of PMOS 124, PMOS 124 is turned on to conduct some ESD current from the stressed input pad to the base terminal of the parasitic PNP BJT 134 in PMOS 132, which is formed by the P+ diffusion, N-well region, and P+ diffusion. With the trigger current injected to the base terminal of the parasitic PNP BJT 134 in PMOS 132, PMOS 132 is turned on to discharge ESD current from the input pad to VDD power rail.
Under positive-to-VDD (PD-mode) ESD stresses, the positive ESD zapping is applied to the input pad while the VDD power rail is grounded and the VSS power rail is floating. Under PD-mode ESD stresses, the parasitic diode formed by the P+ drain diffusion and N-well in PMOS 132 is forward-biased to discharge ESD currents from the input pad to VDD power rail.
Under negative-to-VSS (NS-mode) ESD stresses, the negative ESD zapping is applied to the input pad while the VSS power rail is grounded and the VDD power rail is floating. Under NS-mode ESD stresses, the parasitic diode formed by the N+ drain diffusion and P-well in NMOS 112 is forward-biased to discharge ESD currents from the input pad to VSS power rail.
The same concept can be applied to ESD protection design for an output pad, which is shown in FIG. 2. In FIG. 1, the gate terminals of PMOS 132 and NMOS 112 are connected to VDD and VSS, respectively. However, the gate terminals of PMOS 232 and NMOS 212 are connected to the pre-driving circuit 221 in FIG. 2.
FIG. 3 and FIG. 4 illustrate another ESD protection design proposed in “ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique” reported by M.-D. Ker, T.-Y. Chen, and C.-Y. Wu in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 754-757.
The ESD protection circuit for an input pad is shown in FIG. 3. Under PS-mode ESD stresses, a positive ESD voltage is coupled from the input pad to the floating VDD power rail. Since the capacitor C2 is connected to the grounded VSS power rail, the gate voltage of PMOS Mp2 is initially low enough to turn on Mp2. With the drain current of Mp2 injected into the P-well region of NMOS Mn1, the parasitic NPN BJT (formed by N+ drain diffusion, P-well region, and N+ source diffusion) in Mn1 is turned on to discharge ESD current from the input pad to the VSS power rail. On the other side, under NS-mode ESD stresses, the diode formed by the P-well and N+ drain diffusion in Mn1 is forward-biased to provide ESD protection.
The ESD protection circuit for an output pad is shown in FIG. 4. The gate terminals of ESD clamp devices Mp3 and Mn3 can be driven by a pre-driving circuit. Thus, Mp3 and Mn3 can simultaneously act as an output driver and ESD protection devices. Under PS-mode ESD stresses, a positive ESD voltage is coupled from the output pad to the floating VDD power rail. Since the capacitor C3 is connected to grounded VSS power rail, the gate voltage of PMOS Mp4 is initially low enough to turn on Mp4. With the drain current of Mp4 injected into the P-well region of NMOS Mn3, the parasitic NPN BJT (formed by N+ drain diffusion, P-well region, and N+ source diffusion) in Mn3 is turned on to discharge ESD current from the output pad to the VSS power rail. On the other side, under NS-mode ESD stresses, the diode formed by the P-well and N+ drain diffusion in Mn3 is forward-biased to provide ESD protection.
With the trigger circuits for both PMOS and NMOS transistors, another ESD protection circuit for an input pad proposed in the U.S. Pat. No. 6,566,715 is shown in FIG. 5. The ESD detection circuit 52 is designed to provide trigger current to turn on the parasitic NPN BJT in Mn1 under PS-mode ESD stresses. Similarly, the ESD detection circuit 54 is designed to provide trigger current to turn on the parasitic PNP BJT in Mp1 under ND-mode ESD stresses.
The ESD protection design for an output pad with ESD detection circuits including both PMOS and NMOS transistors is shown in FIG. 6. The ESD detection circuit 80 is designed to provide trigger current to turn on the parasitic BJT in Mn3 under PS-mode ESD stresses. The ESD detection circuit 82 is designed to provide trigger current to turn on the parasitic BJT in Mp3 under ND-mode ESD stresses.